1. Field of the Invention
The present invention relates to a solid-state image-pickup device, a camera system, and a method of driving the same (or belongs to the field of the solid-state image-pickup device, the camera system, and the method of driving the same).
2. Description of the Related Art
A known complementary-metal-oxide-semiconductor (CMOS)-image sensor with a column-parallel analog-to-digital converter (hereinafter, an analog-to-digital converter is abbreviated, as an ADC) mounted thereon had been reported. The above-described CMOS-image sensor is disclosed in “An Integrated 800×600 CMOS Image System” by W. Yang et al., ISSCC Digest of Technical Papers, p. 304-305, February 1999, for example.
The configuration of an example known CMOS-image sensor with a column-parallel ADC mounted thereon is illustrated in a block diagram of FIG. 7.
As shown in FIG. 7, a solid-state image-pickup device 101 includes a plurality of pixels 12, where each of the pixels 12 includes a photodiode and an in-pixel amplifier. The pixels 12 are arranged in matrix form so that a pixel array 11 is generated. A column-parallel ADC includes a comparator 21 and a memory device 51. The comparator 21 compares a reference signal (reference voltages) RAMP generated by a digital-to-analog converter (hereinafter abbreviated, as a DAC) 19 to an analog signal obtained from the pixel 12 for each of row lines H0, H1, and so forth via column lines V0, V1, and so forth. The memory 51 stores information about a result of counting performed by a counter 52 configured to count a comparison-time period. The column-parallel ADC has an n-bit-digital-signal-conversion function. Further, the column-parallel ADC is provided for each of the column lines V0, V1, and so forth so that a column-parallel-ADC block 55 is formed.
Each of horizontal-output lines 16 includes a 2n-bit-wide horizontal-output line, and the 2n sense circuits, subtraction circuit 53, and output circuit corresponding to each of the output lines. Further, a timing-control circuit 20 generating an internal clock, a row-scanning circuit 18 configured to control a row address and row scanning, and a column-scanning circuit 17 configured to control a column address and column scanning are provided, as a control circuit configured to read signals transmitted from the pixel array 11 in sequence.
Next, operations of the example known CMOS-image sensor will be described with reference to a timing chart of FIG. 8 and the block diagram of FIG. 7.
After first reading and transmission of data from the pixel 12 of an arbitrary row line Hx to the column lines V0, V1, and so forth are stabilized, a stepwise waveform obtained by changing a reference voltage over time to the reference voltage RAMP generated by the DAC 19, and the comparator 21 compares the reference voltage RAMP to the voltage of an arbitrary column line Vx. At the same time as when the stepwise waveform is transmitted to the reference voltage RAMP, the counter 52 performs the first counting. When the reference voltage RAMP becomes equivalent to the voltage of the column line Vx, an output transmitted from the comparator 21 is reversed. At the same time, information about the count value corresponding to the comparison-time period is stored in the memory device 51. At the first-reading time, a reset component ΔV is read from each of the pixels 12. The reset component ΔV includes a noise that varies for each of the pixels 12. Usually, however, the variations in the reset components ΔV are insignificant and all of the pixels 12 are reset on the same level. Therefore, an output from the arbitrary column line Vx is approximately known. Therefore, when the reset component ΔV is read for the first time, the comparison-time period can be reduced by adjusting the reference voltage RAMP. In the above-described known example, the comparison among the reset components ΔV is performed over the count-time period corresponding to 7 bits (128 clock signals).
At the second-reading time, the signal component corresponding to an incident-light quantity of each of the pixels 12 is read in addition to the reset component ΔV. That is to say, after the second reading and transmission of data from the pixel 12 of an arbitrary row line Hx to the column lines V0, V1, and so forth are stabilized, the stepwise waveform obtained by changing the reference voltage over time to the reference signal (reference voltage) RAMP generated by the DAC 19, and the comparator 21 compares the reference voltage RAMP to the voltage of the arbitrary column line Vx. At the same time as when the step-wise waveform is transmitted to the reference voltage RAMP, the counter 52 performs the second counting. When the reference voltage RAMP becomes equivalent to the voltage of the column line Vx, an output transmitted from the comparator 21 is reversed. At the same time, information about the count value corresponding to the comparison-time period is stored in the memory device 51. At that time, count-value data obtained through the first counting and that obtained through the second counting are stored in the memory device 51 at different positions.
After the above-described AD-conversion time period, a column-scanning circuit 17 performs the following processing. Namely, n-bit digital signals that are obtained through each of the first counting and the second counting and that are stored in the memory device 51 are transmitted through 2n horizontal-output lines 16, subjected to subtraction processing shown as (the second-counting signal)−(the first-counting signal) in sequence through a subtractor 53, and externally transmitted. After that, the above-described processing is performed for each of the rows so that a two-dimensional image is generated.
In the above-described known example, time changes in the reference voltage are counted. Therefore, the output-bit number is determined according to the number of clock signals of the counter (The number of count-clock signals should be increased by two times, so as to increase the precision of one bit. Subsequently, the output-bit number can be increased only by increasing the clock frequency and/or decreasing the reading speed.